Robust CNFET Circuit Sizing Optimization

Carbon nanotube field-effect transistors (CNFETs) are a promising alternative to CMOS transistors due to the limitation of CMOS toward technology scale-down. In addition to high intrinsic gain, CNFETs can better control current thanks to their unique properties. In this paper, we propose a generic design centering sizing optimization method for CNFET analog circuits. Because of CNFET's low tolerance of parameter variation, our sizing method systematically considers typical process variation in common fabrication practice. By using a modified generalized boundary curve (GBC) method, we strive to boost design robustness and reliability for CNFET analog design. The experimental results exhibit our proposed method's strong efficacy compared to the previous CNFET sizing work.