Bias Temperature Instability on SiC n- and p-MOSFETs for High Temperature CMOS Applications

The circuit functionalities of Complementary Metal-Oxide-Semiconductor (CMOS) devices on 4H-SiC for digital and analog circuit applications beyond 200°C have been extensively studied, however, the reliability of the devices on SiC needs to be demonstrated due to the traps at/near the dielectric interface. In this report, the reliability of n- and p- Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has been studied on three different gate oxide conditions – thick thermally grown, ultrathin thermal + thick CVD oxide and ultrathin thermal + thin CVD oxide in terms of their bias temperature instability (BTI) measurement. The MOSFETs were stressed at various constant bias voltages at 150°C and up to 10
⁵
s. The threshold voltage shift due to positive bias on n-MOSFET is <0.5V after 10
⁵
s at +25Vwhile p-MOSFET shows a larger shift of -1.9V shift after 10
⁵
s at -25V and 150°C for ultrathin + thick CVD oxide. The report also establishes improvement in reliability of p-MOSFETs with ultrathin + CVD oxides over thermally grown oxides.