Degradation Behaviors of 22 nm FDSOI CMOS Inverter Under Gigahertz AC Stress

In this work, Gigahertz (GHz) AC signals are stressed at the input terminal of 22 nm FDSOI inverters and the degradation behaviors of transistors in the inverter are found to be different from that under the single device stress. These transistors work under different bias schemes compared to the regular single device measurements, where the AC stress is applied at the gate and DC stress is applied at the drain. To more precisely characterize the transistor reliability in logic circuits, we design the layout to measure the actual degradation of transistors in the inverter directly. The noise margin of the inverter and SRAM cell comprised of this inverter is also studied. The results in this study show that, in a real inverter, the degradation of pMOSFET is overestimated if the BTI result of single device is used.