A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked Loop for ±10%-SSC Clock-Embedded Display Interface

A clock and data recovery (CDR) circuit based on a multiphase multiplexed recirculating delay-locked loop (MRDLL) is presented for spread-spectrum-modulation clock-embedded display interface. In the training stage, the MRDLL CDR is acting as a phase-locked loop (PLL) to generate sampling clocks. After the PLL is locked, the MRDLL CDR operates as a recirculating DLL to recover the incoming data. Implemented in the 90-nm CMOS process, the chip active area of the proposed MRDLL CDR is 0.118 mm
²
. As a 2.7-Gb/s spread-spectrum signal of 200-kHz modulation frequency and ±10% modulation depth with a triangular-shape frequency modulation is applied, the measured root-mean-square jitter of recovered data and clock is 9.27 and 4.03 ps, respectively. The power consumption is 5.23 mW.