Estimation of Power Consumption in a Network-on-Chip Router

Network-on-Chip is responsible for on-chip communication in multi-core and many-core processors. A Network-on-chip is composed of several routers and channels, each router working on behalf of a processor core or main memory. Buffers, switches, arbiters and allocators are some of the components inside the router of an on-chip network. Along with latency and throughput, power consumed by the interconnection network is a crucial factor to estimate the performance of a processor. In this paper we present a review of power consumption of Network-on-Chip router and its internal components. The majority of the power consumed by a Network-on-Chip router is consumed by the buffers.