Low-Power Dual-Vt 7T SRAM Bit-Cell With Reduced Area and Leakage

This paper proposes a dual-Vt 7T SRAM with a distinct read leakage path. The proposed dual-Vt 7T SRAM features low leakage current because of its single-ended operation which eliminates high power dissipation in comparison with conventional 6T-SRAM. The static noise margin (SNM) for 7T SRAM cells with cell ratio ‘1’ is twice the SNM for conventional 6T-SRAM with cell ratio ‘1.2’. The proposed dual-Vt 7T SRAM bit-cell leakage current was decreased by nearly 50% due to the dedicated read leakage path. By lowering the bit-line activity factor, the dynamic power dissipation is also minimized. To attain the same SNM, the proposed dual-Vt 7T SRAM cell requires the same area as the conventional 6T-SRAM cell. The performance comparisons are made in UMC 180nm technology with a supply of 1.8V. The proposed design has a higher SNM, consumes relatively lesser power, and better read or write stability in the aspect of substantial fluctuations. In comparison to an 8T SRAM cell, the proposed design exhibits 34% less active current. The proposed design is faster than the standard 6T-SRAM cell.