Design alternatives of Network- on-Chip (NoC) Router microarchitecture for future Communication System

The architectures of Network-on-Chip (NoC) are effective fabric for application specific systems-on-chips (SoCs) and general purpose chip multi-processors (CMPs). The important parameters in the design of network on-chip are low latency, high throughput and less area. In order to achieve these goals, NoC router microarchitecture plays an important role. The main drawbacks of Conventional NoC router microarchitecture are circuit complexity, throughput, critical path delay, resource utilization, timing, and power efficiency. The increasing dependence on intellectual properties exposes SoCs to many safetyliabilities and is hovering many concerns. This paper provides an overview of diverse NoC router architecture. The research presented in this paper has investigated different parameters of NoC architecture that are applicable to a wide range of FPGA families.