FPGA Based Implementation of Neural Network

The objective of this paper is to implement a set of Neural Networks (NN) for the detection and recognition of handwritten digit characters. This paper is based on the Modified National Institutes of Standards and Technology (MNIST) dataset which has been used for the testing and training of the NN model. For this application, both software and hardware platforms have been used to obtain efficient outcomes and identify a comparative analysis between the software and hardware performance on the basis of various parameters. These parameters include accuracy, resource utilisation and operating frequency. This implementation of NN has been performed over the software platform using python programming libraries like Tensorflow and Zynet. But studies referring to software-based implementations conclude various limitations in terms of the execution of Convolutional Neural Networks (CNN) as well as NN in computation-intensive, memory intensive, and resource-intensive characteristics of largescale, possessing various challenges. Hence similar techniques have been used to implement the hardware-based results over the Field Programmable Gate Array (FPGA) and to utilize its proficient properties such as parallelism and pipelining for efficient execution. This hardware implementation is achieved through Vivado High Level Synthesis (HLS) software using Verilog programming.