Vertical Tunnel FET Technology: Optimization and Reliability Perspective

This work reports the fundamental concepts on n+ pocket Vertical Tunnel FET (VTFET). An optimization strategy that is applicable to any TFET geometry is presented to optimize its electrical parameters. Furthermore, the optimized device geometry is tested for its reliability under non-ideal situation. Examination of device characteristics has been done considering impact of interface trap charges. Two types of trap charge distributions viz. uniform and Gaussian are taken into account. Temperature affectability is also studied to find out the range of operating temperature of the device. Finally, the RF characterization of the device is carried out to check its viability in high frequency applications.