A W-Band SPDT Switch With 15-dBm P1dB in 55-nm Bulk CMOS

Power-handling capability of bulk CMOS-based single-pole double-throw (SPDT) switch operating in millimeter-wave (mm-wave) and subterahertz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network (ITN) is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70–100-GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss (IL) of 3.5 dB, and an isolation (ISO) of 18 dB. The total area of the chip is only 0.14 mm
²
.