FPGA Implementation of FBMC Transceiver for 5G Technologies

Filter bank Multicarrier (FBMC) is a clever procedure developed from OFDM which settle the vast majority of these issues by adopting a separating strategy to multicarrier correspondence framework. FBMC signs can undoubtedly meet the Adjacent Channel Leakage Ratio (ACLR) and they don't utilize cyclic prefix in this manner works on unearthly effectiveness. Because of the incorporation of band-restricted heartbeat molding channels into the sign model in FBMC procedure, the plan of effective handset designs for multicarrier frameworks turns into a difficult errand. An efficient FBMC hardware architecture is designed and implementation is presented. It includes both transmitter and receiver. The design uses pipelined 8-point IFFT/FFT and polyphase filter (PP-F) for the processing at transmitter and receiver module respectively, which indicate that the processing block contain 8 inputs data. It also includes serial to parallel and parallel to serial converter module. Finally, comparative performance analysis of proposed FBMC system over OFDM systems is performed in terms of Signal-to-noise ratio (SNR), Bit error rate (BER), Latency and Throughput. The Results show that proposed FBMC transceiver is better in terms of performance, hardware complexity overhead and power consumption as compared to OFDM system.