Nonlinear Function Acceleration Based on FPGA Heterogeneous Platform

To solve the problem that the convolutional neural network model is limited by the resources of the embedded platform, this paper proposed and designed a target detection platform accelerated by a heterogeneous chip based on FPGA . The platform uses FPGA heterogeneous chips to accelerate the compressed yOLO v2 model. In the compression process, channel pruning is used to remove the redundant channels in the convolutional neural network model and reduce the model parameters to save the hardware storage resources. The hardware platform adopts Xilinx Pynq-Z2 board and the image is preprocessed by ARM. Then, the processed image data and model parameters are transmitted to FPGA through AXI bus for layer by layer convolution network acceleration. Aiming at the implemented acceleration platform, the implementation mode of nonlinear function operation in FPGA is further studied to optimize the acceleration effect. The experimental results show that the average processing time of each image is 530ms and the average precision is 0.7582 after adding PE split cache data pipeline, which is 20ms faster than that without PE split cache data pipeline. A part of the nonlinear operations is fitted in FPGA by function mapping method or segmented Taylor expansion to achieve greater acceleration.