Comparative Analysis of Different Types of Inverters for Low Power at 45nm

VLSI is an evergreen field that is constantly expanding. To fit more gates on a given chip area, a significant amount of work is required. As a result, removing the heat generated is difficult. Using low-power circuits, this problem can be solved. In today’s electronics industry, a low power requirement has become a primary goal. In the design of VLSI chips, power dissipation has become as critical as performance and size. Low-power chip requirements are becoming increasingly important in the VLSI business as chip dimensions shrink and environmental issues become more important. Because of the requirement to low package cost and increase battery life, power optimization is as critical as time for many systems. In the past, the total power dissipation of CMOS devices was dominated by dynamic power. This paper discusses CMOS, lector, forced NMOS, forced 2 NMOS, forced PMOS as approaches for reducing power requirements at various stages of CMOS architecture. The results are examined at various supply voltages while maintaining the load capacitance (C
load
= 500fF) which include power, delay, switching threshold voltage, noise margin, the inverter utilizing forced NMOS technology is considered good because the noise margin obtained is the highest here, 2.48V evaluated at 4.02V supply voltage. When all other factors are equal, the inverter adopting the lector approach consumes less power than the other inverters at all supply voltages.