Design of High Speed, Energy, and Area Efficient Spin-Based Hybrid MTJ/CMOS and CMOS Only Approximate Adders

It is important to explore better alternatives to CMOS to sustain Moore’s law far in the future. One option is to integrate non-volatile spin devices, such as magnetic tunnel junction (MTJ), with the existing CMOS technology to augment its capability. This article presents five approximate 1 bit full adders for applications where accuracy can be traded for energy, speed, and area. The application of an approximate adder is demonstrated in image processing for smoothening an image. Three of these adders are fully non-volatile, one is partially volatile, and one is fully volatile. All the adders use SRAM-based sense amplifier (SA) to reduce sensing energy and hardware count. To reduce the delay, some of the adders utilize the parallel connection of logic devices (MTJ or MOSFET) in the logic tree. All the adders are simulated using 45 nm CMOS predictive technology model (PTM) and perpendicular magnetic anisotropy (PMA) CoFeB/MgO/CoFeB MTJ model with HSPICE simulator. After performing simulations, results show that the proposed fully non-volatile approximate adder (AXFA4) performs exceptionally well against its existing counterpart AX_MFA2 in terms of the energy-delay product (EDP) and the area-delay product (ADP) with a decrement of 84% and 80%, respectively. All the adder designs compute sum at 75% and carry at 100% accuracy, respectively.