A Fault Diagnosis Technique of SMGFs in $k$-CNOT Based Reversible Circuits

This paper introduces a fault diagnosis technique to obtain the exact location of Single Missing Gate Faults (SMGFs) in
$k$
-CNOT based reversible logic circuits. The proposed fault diagnosis technique establishes that the generated single test vector can identify the exact location of SMGFs. For this purpose, we construct the augmented circuit that behaves as Circuit Under Test (CUT) and the testable augmented circuit is used for detecting the SMGF faults. The parity checking operations are included in the constructed augmented
$k$
-CNOT circuit to obtain the exact location of SMGF. Finally, this paper presents the experimental results and analysis in order to show the effectiveness of determining the exact location of faults in a
$k$
-CNOT circuit.