Physical Design and Implementation of Lakshya -Sub-system of Built in Self Test System

The Integrated Circuits (IC) designed today are complex and hence require a good Physical Design strategies and optimization. Physical Design process involves placing all components including standard cell and macros inside the core area of the integrated circuit. “Lakshya” is the name given to the sub-system of the Finite State Machine (FSM) based programmable memory Built in self-test (BIST) with macro command. It is created with an intent to capture the various aspects and challenges of the VLSI design flow. It is meticulously planned to expose the real-world complexities in physical design which consists of submodules such as Microprocessor Core, Image Processor Core, Cryptography Core, Direct Memory Access Control (DMAC) Controller, Data Manipulation Core, Communication Core. The specifications of the Lakshya Sub-System include supply Voltage of 1.1V, sub-system area 4.2 square mm, Clock frequency of 833MHz, Power consumption under 600mW and Max IR drop of VDD and VSS 5%. Assumptions are initial Core Area Utilization ratio of 67.21% and Core to Die Boundary Spacing is 3um. Considering all the above specifications, physical design and implementation was carried out successfully involving Floorplanning, Power planning, Placement, Clock Tree Synthesis, Routing and Static Timing Analysis. All the steps in Physical Design significantly affect circuit timing and performance. The Physical Design and Implementation was carried out using Synopsys Design tool IC Compiler II. The technology node used was 40nm. The contribution of in built algorithms of the tool and also the skill of designer is important to optimally place and interconnect large number of Components.