High Audio Band PSR and Fast Settling-Time Dual-Loop LDO Regulator Architecture for Low-Power Application

This paper presents a fully integrated 65nm CMOS Low-Dropout (LDO) voltage regulator for MEMS devices in the microphone field. The proposed LDO exploits a nested loop to generate the regulated voltage. The external loop generates a precise
$\mathbf{V}_{\mathbf{out}}$
and the internal loop gets a fast transient response by means of a Flipped Voltage Follower (FVF). To achieve a high Power Supply Rejection (PSR) a Tail compensated Error Amplifier (EA) was used. Powered by
$a$

${1.8\mathrm{V}\pm 10\%}$
VDD, the LDO provides a 1.2V regulated voltage in the whole temperature range
${[-40, 85]^{\circ}\mathrm{C}}$
while consuming a quiescent current of 8.7uA (15. 7u W of nominal power consumption). It is capable of driving from 200uA to 800uA of static current load without affecting performance. The LDO occupies an active area of
${0.0363\text{mm}^{{2}}} {(0.3\text{mm x}\ 0.121\text{mm})}$
including the 70pF on chip capacitor. This means that the LDO can be used in a System on a Chip (Soc) thanks to the absence of an off-chip capacitor. The simulation shows a PSR
${< -70\text{dB}}$
in the audio band ([20, 20k]Hz), a PSR peak below -10dB and a fast transient response of 148ns. Furthermore, Montecarlo and PVT simulations show the robustness of the circuit. Worst cases prove that the
$\mathbf{V}_{\mathbf{out}}$
value never exceeds
${1.2\mathrm{V}\pm 5\%}$
during DC and transient analysis. The overall
$\mathbf{V}_{\mathbf{out}}$
error is 0.3%.