Simulation and Performance Analysis of Hetero Dielectric Underlap Asymmetrical Double-Gate MOSFET Using Gate Stack

Lately, underlap DG-MOSFET with gate stack technology has been accredited for its redemption over short-channel-effects in the Nano scale regime. In this work, a simulation-based study of hetero dielectric underlap asymmetrical double gate MOSFET with gate stack is presented in the 50 nm gate length regime. Visual TCAD simulator is used to design and simulate the proposed device. Using the extensive device simulations in 2-D visual TCAD, the smeared MOSFET has been simulated to investigate the impacts of different performance parameters such as the threshold voltage, drive current, gate leakage current, ON/OFF current ratio, subthreshold-swing, drain induced barrier lowering, transconductance, center/surface potential, center/surface electric field. It has been observed that the proposed hetero dielectric U-AS-DG-GS MOSFET shows good agreement with these simulation results comparing other state-of-the-arts at 50 nm technology node.