A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment

This paper presents a 2×VDD, PVT-insensitive (process, voltage, and temperature) output buffer that has a slew rate and duty cycle self-adjustment. It complies with the slew rate, system voltage, and duty cycle requirements for DDR4 SDRAMS. Low Vth transistors which are always turned on are selected as drivers in the output stage to prevent output current fluctuations and increase the driving current. These transistors' gates are stabilized by both driving currents and a capacitor rejecting any interference by the noise coupled from GND. The output buffer is realized using TSMC 16-nm FinFET CMOS process. The core area is
$0.1412\times 0.0794\ \text{mm}^{2}$
. At 2.5 GHz, it has maintained a slew rate of 6.4 and 8.7 V/ns and a duty cycle of 48.3 to 49.2% at a maximum load capacitance of 30 pF. Whether at normal voltage mode (VDD) or high voltage mode (VDDIO), the improvement in slew rate increase (
$\Delta\text{SR}$
improvement) is approximately at least 20% after driving current auto-tuning.