Design of Common DC-Link Capacitor in Multiple-Drive System Based on Reduced DC-Link Current Harmonics Modulation

Many industrial applications are recently utilizing the advantages of a common dc-bus-based multiple-drive (multidrive) system, such as low installation cost, space savings as well as improved reliability, and flexibility. One of the main drawbacks of such systems is the requirement for a bulky dc capacitor due to the presence of large dc-link current ripples from the harmonic interaction between these multidrive and pulsewidth modulation (PWM) switching. This problem not only increases the cost and volume of the dc-link capacitors but also decreases its lifetime, which must be considered in the design from the industrial aspect. This article proposes a new dc-bus capacitor design method for a multidrive system, focused on the capacitor sizing, cost reduction, and lifetime improvements. First, an analytical model to obtain the dc-link capacitor current in a multidrive system is proposed, which would aid the designers to configure the dc-capacitor current in systems having numerous multiple drives. Next, using the developed analytical model, the dc-link current harmonics are reduced through optimal interleaving of the fundamental output currents in addition to the phase shifting of the carrier waves of the parallel connected inverters. Finally, new capacitor sizing/design is proposed considering the lifetime, power loss, cost, and volume of the dc-link capacitor bank. The proposed approach reduces the volume and cost of dc-cap bank by 50%, and increases the lifetime by four years (
$\sim$
35 000 h), considering the worst-case scenarios. Experimental and analytical results are given for validation of the proposed method. The results could serve as a guideline for designing the dc-link capacitor in multidrive applications in a low-cost manner.