Design and Realization of FPGA-based DRFM with High Instantaneous Bandwidth

Modern target simulators adopt the DRFM as the core architecture to quickly and accurately reproduce and transmit complicated radar signals. This paper introduces an FPGA-based DRFM architecture with high instantaneous bandwidth, which utilizing efficient polyphase decimating and interpolating technique with sampling rate up to 5GSPS to design the parallel digital down-conversion (DDC) and digital up-conversion (DUC) modules, realizing the digital demodulation and modulation of the baseband signals. The introduced DRFM architecture can achieve the radar target simulation by receiving the broadband signals and then transmitting them after digital processing. Moreover, integrating the simulation functions of target echo signals and interference signals in FPGA, this architecture can realize multi-target and multi-functional design of radar target simulation, facilitating to evaluate of the anti-interference performance of the radar system.