Performance Analysis of Stack Gate Oxide Underlap TFET Utilising Metal Strip Mechanism

To overcome the performance degradation due to underlap in Stack Gate Oxide Tunnel Field Effect Transistors is the most crucial issue. Thus to ameliorate the performance of stack gate-oxide tunnel field effect transistor with underlap at the gate-source region, implantation of metal strip with low work function in the oxide region is proposed in this work. The simulation graphs show that the stacked device with live metal strip namely Low Work Function Live-Strip-Dual-Material Gate-Oxide-Stack Double-Gate TFET (LWLS-DMGOSDG TFET) performance is better than conventional DMGOSDG TFET with regards to performance parameters such as charge concentration, energy band, transfer characteristics and electric fields. These are the few graphs which proves the applicability of the device with regards to DC electrical Figure of Merits (FoMs). The device simulation has been performed in semiconductor device design simulation tool, 2D-TCAD by Synopsys.