Computational study for electronic interconnects and performance of solders and solder paste

The interconnect contacts consisting of solder act as bottleneck in terms of reliability in electronic chips. Computations have been performed to investigate the efficacy of solders considering traditional ones and solder paste. The study focuses on solders and solder paste that can operate at various thermal load and material structures. In this study, Quilt Packaging, QP, Thru Silicon Via, TSV, and Flip chip structures have been utilized to find the effectiveness of the solders. The electroless solder or solder pastes are applied in narrow interconnect as done in quilt packaging, whereas other solders are used in wide connections that can carry substantial currents as observed in traditional interconnects. The chip as well as the interconnects can generate heat during operation; specifically, in hot spots, it can produce large temperature gradient resulting in increased thermal stress. The simulation demonstrates structural deformation due to dielectric or resistive heating. With the available fatigue parameters for the solders, plastic strain and failure have been computed for the structures. Finally, with the mentioned constraints, the simulation results indicate the material parameters to focus on when selecting solders.