A Novel Fourth-Order Multi-Bit Quantization ΣΔ Modulator

Based on the structure of fourth-order single loop multi bit comparator, a high-precision digital discrete-time sigma delta (DT ΣΔ) comparator is designed. The modulator using CIFF architecture, by optimizing the modulator parameters, CIFF structure can effectively reduce the number of feedback DAC, and avoid the oversaturation problem of each stage integrator. At the same time, multi-bit quantization and feedback are introduced in the loop. MATLAB/Simulink model is built for system analysis, and PSO (particle swarm optimization) algorithm is used to optimize the parameters at all levels. Simulation results show that the proposed method can effectively suppress the influence of non-ideal factors in signal transmission process, reduce quantization error, improve system stability and signal-to-noise distortion ratio, and reduce hardware cost and power consumption. Finally, the hardware structure of the system is established by using ARM embedded chip, and the hardware test is completed. The simulation results and test results verify the effectiveness and superiority of the proposed ΣΔ modulator.