Controlling Threshold Voltage of CMOS SOI Nanowire FETs With Sub-1 nm Dipole Layers Formed by Atomic Layer Deposition

In this article, bidirectional control of threshold voltage ( ${V}_{T}$ ) is realized in both n- and p-silicon-on-insulator (SOI) nanowire FETs (NWFETs) by using sub-1 nm atomic-layer-deposited (ALD) dipole layers (Y₂O₃ and Al₂O₃) for the first time. A 0.7 nm Y₂O₃ inserted between bottom native SiO_x (< 1 nm) and top HfO₂ (3 nm) can shift the ${V}_{\text {TH}}$ by −138 and −58 mV for n- and p-NWFET, respectively, while 0.7 nm Al₂O₃ can shift the ${V}_{T}$ of n-NWFET by +219 mV and p-NWFET by +134 mV. The tunability of such a high-k superstructure for the flat band voltage ( ${V}_{\text {FB}}$ ) shift of capacitors and ${V}_{\text {TH}}$ shift of planar n-SOI FETs are also investigated. Furthermore, to concisely control the ${V}_{\text {TH}}$ and ${V}_{\text {FB}}$ as design, capacitors fabricated with quadra-layer (SiO_x/HfO₂/Al₂O₃/Y₂O₃) high-k superstructure were fabricated and 3 mV ${V}_{\text {FB}}$ shift is achieved by carefully adjusting the composition of intermixed-dipole layers. This work points out the route to concisely tune the threshold voltage of complementary metal-oxide-semiconductor (CMOS) FETs with the desired direction and strength.