Hardware Optimization and FPGA Implementation of Pipelined ZUC Architecture

The ZUC stream cipher belongs to synchronous stream cipher category. The cipher is word oriented and produces two words (32-bits) cipher text per cycle. The ZUC uses 128 bits key and 128-bits Initialization Vector (IV) for its operation. The research work considers FPGA implementation of pipelined ZUC architecture. The presented work uses compact architecture for modulo adders (over 2
³¹
-1) used in feedback path and modulo adders (Over 2
³²
) used in Finite State Machine (FSM). It also uses novel S-box architectures to minimize hardware resources. The presented architecture coded using VHDL language using Xilinx ISE 14.2 software for synthesis and simulation. The hardware implementation of the design uses Xilinx FPGA Virtex-5 XC5VFX130T having package FF1738. The presented hardware attained throughput of 5411.8 Mbps at clock frequency of 169.119MHz. The result shows the considerable hardware optimization.