Embedded STT-MRAM Energy Analysis for Intermittent Applications using Mean Standby Duration

Power, area, and delay trade-offs occupy a vital role in early pre-fabrication design decisions for various System-on-Chip (SoC) and intermittently powered devices. The approach taken herein is to explicitly incorporate device technology trade-offs during the initial circuit design process. Specifically, the asymmetry between read/write energy consumption and active/standby duty cycles are used to facilitate trade-offs between use of embedded 6-Transistor Static Random Access Memory cell (6T-SRAM) versus embedded Magnetic Random-Access Memory (MRAM)-based on Spin Torque Transfer Magnetic Tunnel Junction (STT-MTJ) single bit cell structure of two transistors and one MTJ (2T-1R). A model is developed and validated to estimate power in hybrid Complementary Metal Oxide Semiconductor (CMOS)/MTJ technology with coefficient of determination
$\mathrm{R}^{2} > 0.95$
. The approach employs three new metrics: Mean Standby Duration (MSD), Mean Active Duration (MAD), and Power Dissipation Scaling Ratio (PDSR). Thresholds of
$\text{MSD} > 0.995$
and
$\text{MAD} < 0.005$
were determined to be inflection points for lifetime energy justification for considering MTJ devices in terms of total power. Results substantiate a transportable approach for the inclusion of emerging logic devices by considering the energy profile of some intermittently powered applications by parameterizing the workload using the metrics defined herein.