High Performance Variable Precision Multiplier and Accumulator Unit for Digital Filter Applications

The computationally intensive designs such as Multiplier Accumulator Unit need to be revisited for ascertaining better performance. Design of MAC unit using Variable Precision multiplier is explored in this paper with adoption of this concept to multipliers like Array, Carry Save, Booth and Vedic Multipliers. The variable precision MAC unit saves the computation memory as the partial results are computed with less memory so that the final result has a size of 2n x m for multiplication of n x m bits. The Verilog HDL modeling is used for the designs and Xilinx ISE 14.5 with ISIM simulator are used to functionally verify for Zynq 7000 series FPGA (XC7Z020-1CLG484). Among these, Vedic VPMAC FIR Filter proved to be better for area and delay by atleast 23.05% and 17.16% respectively, with a trade-off of 2.04% in power dissipation when compared with the other three designs. Also when compared with existing designs, it uses less area, delay and power dissipation by at least 8.06%, 8.58% and 2% respectively.