ESD-capability Improvement of Ultra-high Voltage nLDMOS Components by the Drain Side Engineering

A TSMC’s $0.5-\mu m$ UHV 300-V LDMOS process is used to fabricate ESD protection components, which are divided into three categories. The first group is doped with the Sh_p layer under the drain $N^{+}$ electrode of the original reference device. For the group-2, the $N^{+}$ drain terminal of the reference device was changed to $P^{+}$ and the Sh_p layer was doped under the $P^{+}$ of the drain terminal. Here, changing the width of $N^{+}$(LN) and P+(LP), and the Sh_p and metal layer were formed a heterojunction. Then, the device’s V
h
value of the UHV LDMOS can be improved through a heterojunction diode in series, and the ESD capability can be enhanced. In group-3, the Sh_p layer is added in the drain side. The main purpose of this is to compare the effects of Schottky and heterojunction surfaces formed at different positions in the devices. This is because the addition of the heterojunction will increase the V
h
value. This allows us to achieve the maximum FOM and ESD ability in different locations. Firstly, we measured the breakdown voltage of the three designed components. The trends and results were compared with the reference component. Three different ways of adding the Sh_p can be found that there is almost no change compared to the reference group. Next, the snapback characteristics of these power components will be measured by a TLP tester. For the group-1 samples, when the $N^{+}$ width is 6.5$\mu$m(SHP_ LN_ 6.5), the ESD (secondary breakdown current; I
t2
) ability is increased from 1. 723A (the original reference device) to 4. 216A. Next, for the group-2 samples, when the $P^{+}$ width is 13$\mu$m(SHP_LP_13), the I
t2
value can be increased to 3.729A. This allows us to compare the maximum FOM and ESD values that can be achieved by different arrangements. Finally, in group-3, the maximum FOM value is achieved when the component is ref_H
S_
N, where the I
t2
can reach 4. 95A.