A Fast method to predict the Voltage Droop for Fully Integrated Voltage Regulators in Microprocessors

Modern high performance server microprocessors processors have built-in Fully Integrated Voltage Regulators (FIVR) to generate the on-chip power domains. FIVR is designed using on-Die power MOSFETs, package inductors, on-Die capacitors, and feedback control circuits. High di/dt events on the output of FIVR domains lead to large voltage droops which affect the circuit performance. This voltage droop needs to be modelled accurately and minimized in the design stage. Frequency domain-based analysis is typically followed in industry to optimize the design parameters such as the Gain margin, Phase margin, and the unity gain bandwidth of the feedback loop. However, it is difficult to predict the time-domain parameters such as the voltage droop and the peak time using the frequency domain methods. In this paper, a fast method is proposed to predict the voltage droop for FIVRs in time domain using analytical methods. The proposed method helps to easily do a sensitivity study of the different control variables on the voltage droop and reduces the time needed for optimal design.