An Area and Power-Efficient Cubic Array Multiplier Exploring Parallel Prefix Adders

This paper presents a new area- and power-efficient cubic array multiplier based in 12 logic optimization steps in the partial product matrix and also explores Parallel Prefix Adders (PPA) in the addition tree. The implementation of the optimized cubic multiplier uses only the essential addition trees, avoiding thus, redundant operations. It is possible because, in this type of circuit, some multiplications are sometimes triplicated and can be discarded through logical simplifications. The use of PPA further reduces the complexity required by the sums of the partial product lines. All the architectures of this work were described in VHDL and synthesized for ASIC using the ST 65nm standard cell library. The results show that the proposed multiplier presents gains in both power dissipation of 7.41% and area of 38% when compared with the state-of-the-art cubic multiplier. The results also show that the proposed multiplier using the Kogge Stone adder saves up to 21.64% in power dissipation and 8.88% in the cell area when compared to other PPA adders.