Investigation on the Accuracy of the VSD-Method for Different SiC MOSFET Designs Considering Different Measurement Parameters

During power cycling tests, a precise junction temperature estimation is necessary for a correct interpretation of the test results and it is even more important, when the test results are used for lifetime modeling. For SiC MOSFETs, a common approach is to use the VSD-Method, which was reported to deliver accurate junction temperature readings. However, given the variety of device designs and technologies available on the market, this cannot be taken for granted for all SiC MOSFETs. For that purpose, different aspects of the accuracy of the VSD-Method were investigated in this work, by comparing the junction temperature reading obtained by the VSD-Method, with the actual chip temperature, measured by thermography for two different SiC MOSFET designs. Whereas one design lead to accurate temperature readings, the other exhibited a significant deviation between the temperature measured by thermography and the temperature reading by the VSD-Method. Furthermore, the impact of the gate voltage on the temperature reading of the VSD-Method was investigated. Both designs exhibit a consistent temperature reading for gate voltages 2V above and below the maximum rated negative gate voltage for a wide range of sensing currents. Hence, the results show, that a systematic measurement error can occur for some SiC MOSFET designs, which may cause a misinterpretation of power cycling test results. Therefore, it is important to verify the accuracy of the temperature estimation when deploying the VSD-Method for SiC MOSFETs, particularly when comparative tests are performed or the test results are used for lifetime modeling.