A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS

Recently, a receiver (RX) is demanding a high bandwidth data rate. Multi-level signals such as four-level pulse amplitude modulation (PAM-4) are more advantageous than two-level PAM (PAM-2) to meet the required bandwidth. However, the multi-level signals reduce the amplitude of the main cursor (ho), are more affected by inter-symbol interference (ISI), and especially pre-cursor ISI is hard to cancel on RX. Thus, the RX needs a phase detector (PD) that controls pre-cursor ISI to obtain the bit-error rate (BER). On the other hand, a clock and data recovery (CDR) utilizes a Mueller-Muller PD (MMPD) as a Baud-rate PD (BRPD) for power efficiency and reduced clock overhead. However, the MMPD moves a lock point where a first-tap pre-cursor ISI (h-1) becomes zero with an adaptive decision feedback equalizer (DFE) [1]. It makes the CDR vulnerable to noise or causes the lock point to drift. To move the lock point $h_{1}=h_{-1}\neq 0$, PDs which add a phase offset are proposed [2],[7]. However, it does not secure a vertical eye margin (VEM) in the multi-level signal, although the adaptive DFE exists. In this paper, a BRPD that is more compatible with multi-level is proposed. The PD locks a point that h
0
becomes $\mathrm{N}_{\mathrm{t}}\cdot h_{-1}$ where $\mathrm{N}_{\mathrm{t}}$ is a target cursor ratio. The $\mathrm{N}_{\mathrm{t}}$ secures a VEM by controlling h-1 states. Furthermore, the lock point is independent of post-cursor ISIs, and thus, the PD with an adaptive DFE has a unique lock point.