A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE

The memory I/O interface needs to achieve two conflicting requirements: increasing I/O bandwidth and reducing energy consumption at the same time. To achieve these goals, memory interface is now rapidly moving from Non-Return-to-Zero (NRZ) to Pulse Amplitude Modulation-4 (PAM-4) [2]. However, the test infrastructure for PAM-4, such as ATE, which is the most important factor in memory mass production, has not yet been established, and only NRZ can be supported. In this paper, we propose a PAM-4 Built-Out Tester (P4-BOT) that can perform PAM-4 mass production test using the ATE that supports NRZ only. The P4-BOT device converts PAM-4 into NRZ signals with single-ended Low Voltage-Swing Termination Logic (LVSTL) with maximum operation speed 24Gb/s/pin. The P4-BOT supports four different operation modes, (i)PAM-4 to NRZ 2-pin, (ii) NRZ 2-pin to PAM-4, (iii) PAM-4 to NRZ 1-pin, and (iv) NRZ 1-pin to PAM-4 as shown in Fig.1. To achieve high performance, we implement, (1) The hybrid WCK scheme [1] capable of switching between CMOS (low frequency) and CML (high frequency) mode, (2) the active inductor to increase speed of the WCK CMOS buffer, (3) the LDO to reduce Power Supply Induced Jitter (PSIJ) of WCK.