A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS

This brief presents a 32-way 6b 48-GS/s asynchronous time-interleaved ADC. To enhance sub-ADC conversion speed, 2b/cycle asynchronous SAR ADC is adopted for sub-ADC structure, which can operate at 1.5-GHz. Instead of using reference DAC, 9 built-in reference samplers are employed for 6b 2b/cycle operation. Interleaver incorporates 8 sample and hold amplifiers (SHA) and each SHA drives 4 sub-ADCs. Core ADC uses 1 V supply and the interleaver uses 1.1V supply to secure the linearity of the switches. The proposed time-interleaved ADC has been fabricated in 28-nm CMOS technology and occupies an active area of 0.3565 mm
²
. The ADC consumes 72.3mW at the sampling rate of 48 GS/s, including clock distribution power.