A Power-efficient Implementation of SHA-256 Hash Function for Embedded Applications

SHA-256 is a well-known algorithm widely used in many security applications. The algorithm provides a sufficient level of safety and can be performed efficiently by FPGA devices due to its high parallelism level. This paper presents a high-throughput, low hardware resources usage, and power-efficiency architecture of the SHA-256 algorithm targeting FPGA-based embedded platforms. The SHA-256 computing core takes advantage of the specific architecture of FPGA to achieve high performance. We implement the SHA-256 computing core with hardware description languages so that the computing core is technology-independent. Therefore, the computing core is suitable for building applications with various FPGA-based platforms. We conduct several experiments with both simulation and SoC boards. The experimental results show that the core achieves the same functionality, performance, and power consumption when implemented on different FPGA families. The implemented system with our SHA-256 computing core can function at 139.04 MHz, achieving a bandwidth of up to 1.04 Gbps. The SHA-256 computing core is power-efficient when consuming only 0.072 W with the minimum configuration.