Impact of metal grain granularity on three gate-all-around advanced architectures

The impact of metal grain granularity (MGG) on the threshold voltage $\left(V_{T h}\right)$ is compared for three different CMOS nanoscale multi-gate architectures with similar dimensions. The MGG of the gate stack induces the most pronounced variability in the device characteristics of non-planar architectures. We use the fluctuation sensitivity map (FSM) technique to evaluate which part of the channel beneath the gate is more affected by the MGG variability, and carry out a statistical study of the correlation between $V_{T h}$ and the effective mean work-function (WF) of the gate. The nanosheet (NS) FET turns to be the most resilient architecture to the MGG with a threshold voltage standard deviation $\left(\sigma V_{T h}\right)$ of 104% and 54% lower than those of the nanowire (NW) FET and the FinFET, respectively.