Multi-Domain Ferroelectric FETs with Negative and Enhanced Positive Capacitance for Logic Applications

In this paper, we analyze the multi-domain (MD) ferroelectric FET (FEFET) as a non-hysteretic transistor with enhanced gate control for standard logic applications. We consider two regimes of operation i.e., when the ferroelectric (FE) layer acts as (1) an effective negative capacitor (NC) under soft domain-wall (DW) displacement and (2) an enhanced positive capacitor (EPC) in case of hard-DW with no displacement. Our analysis is based on the self-consistent 2D phase-field simulation of FEFET considering HZO as the FE layer. We analyze the MD induced non-homogeneous potential profile in FEFET and show that the MD NC and EPC phenomena lead to an improvement in the subthreshold-swing and mitigation of other short-channel effects compared to the conventional high-k FET (HKFET). Moreover, the presence of domain-wall (DW) and non-homogeneous potential profile in the FEFET channel leads to a unique transport and a robust gate length scaling behavior compared to the HKFETs, which signifies the benefits of MD FEFET for future scaled FET technologies.