Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET

The Fully-Depleted Silicon On Insulator (FDSOI) technologies are deployed for a wide range of applications (digital, analog, RF, etc.) requiring a large variety of MOS transistors. These transistors are defined by several dedicated specificities such as their threshold voltage or their gate oxide thickness. Usually, the surface potential (SP) based compact model of FDSOI MOSFET supposes an undoped channel with metal gate in front and back contact [1–3]. These models are not sufficiently accurate for real devices; thus, in the modern compact models [1–3], a lot of parasitic effects must be included such as the substrate depletion. This paper describes the recent improvements of L-UTSOI standard model, with the introduction of the poly-depletion effect and an enhanced model of the substrate doping effects. These model extensions are validated against silicon experimental data and available in the latest official model release.