A 1.17ns FO4(1V) Low Energy Cost 4-Bit Absolute-Value Detector

Traditionally, absolute value detectors are time-consuming and not precise enough, which will cause some trouble in the CMOS circuit. The first trouble is that we will use too many components. We divide the traditional absolute value detector circuit into two steps. The first step is to get an absolute value, and the second step is to compare the absolute value with the given threshold voltage. Among these steps, we will use many multiplexers and full adders. So, both the delay and the energy cost will be overgrown. The second trouble is that the output might be wrong because the output of these comparators cannot be perfect 1 or 0 volts but only be a number between them. This feature might lead to some incorrect results when the input is near the middle points. If one tries to make a circuit without this drawback, the circuit will use many CMOS units, which will cause a considerable energy cost. Because of such significant drawbacks in traditional circuit structure, we find it necessary to design a new kind of circuit with better performance. So, we propose an innovative configuration and optimize it with logic effort theory. What we use to take the place of the two steps is a mirror adder. The mirror adder is an improved adder circuit. Firstly, it eliminates the carry inversion gate; secondly, the PUN and PDN network of the gate is no longer dual but cleverly realizes carrying propagation. By using this, we successfully reduce the delay and restrict the power consumption within a specific range. In addition, we innovatively apply logic effort theory to optimize our circuit. The final delay is 1.17ns, which is low compared to the traditional method in the same circumstance. Further, we use fewer components, so the consumption of power is less than the traditional two. Our optimized circuits significantly reduce the amount of CMOS required, which will result in a lot of energy reduction and give more LOT devices a longer standby time.