Advancing Monolayer 2-D nMOS and pMOS Transistor Integration From Growth to Van Der Waals Interface Engineering for Ultimate CMOS Scaling

2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore’s Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness and manufacturable CVD, molecular beam epitaxy (MBE), or seeded growth. nMOS devices on transferred MBE MoS
₂
using novel contact metal show low variation, one of the lowest reported contact resistances (
${R}_{\text {c}}$
) of 0.4
$\text{k}\Omega \cdot \mu \text{m}$
, low hysteresis, and good subthreshold swing (SS) of 77 mV/dec. pMOS devices using CVD WSe
₂
show 89 mV/dec SS, best reported for pMOS on grown films, but ON-current remains behind nMOS. We show
${R}_{\text {C}}$
is improved by
$5\times $
by using a bake process prior to contact metal deposition. Transfer-free, area-selective seeded growth techniques for WS
₂
and MoS
₂
are demonstrated as options for wafer-scale TMD channel growth. WS
₂
transistors achieve 10
$\mu \text{A}/\mu \text{m}$
ON-current, highest reported on WS
₂
using seeded growth. A new capacitance method is shown to monitor 2-D material contact interface quality. Gate-oxide interface engineering through metal seeding and atomic layer deposition (ALD) demonstrates that a single 2-D channel material can selectively make pMOS or nMOS transistors, alike Si CMOS, and can also be used as a method to achieve p-type doping. We compare back-gated bare channel devices with dual-gate devices and observe hysteresis-free operation and an improvement in mobility with proper passivation.