A Lightweight and Real-Time Hardware Architecture for Interference Detection and Mitigation of Time Synchronization Attacks Based on MLP Neural Networks

Stationary GPS receivers provide time information for critical infrastructures, such as phasor measurement units (PMUs), communication networks, and financial systems. Therefore, they are prone to a specific type of spoofing attack called time synchronization attack (TSA), which affects time information such as clock offset and clock drift. The receiver’s position remains constant during the attack; hence, attack detection and mitigation are challenging. Various countermeasures have been suggested to mitigate TSA effects. However, they are mainly software-based and are exploited to protect software implemented software-defined radios (SDRs). In this research, two hardware protection approaches are contributed for hardware-based SDRs based on multi-layer perceptron neural network (MLP NN) with sigmoid activation function. The most challenging part of MPL NN implementation is the activation function approximation. Therefore, two lightweight architectures are proposed for sigmoid function implementation. Linear approximation and look-up table (LA-LUT) and piece-wise linear approximation (PLA) are exploited for this task. The synthesis results demonstrate that the PLA approach has a slightly higher resource utilization in comparison to LA-LUT, while this method is more accurate. The mean squared error (MSE) of the PLA approach is equal to 0.019, which is 57% better than the LA-LUT approach with an MSE of 0.033. Furthermore, the designs are evaluated by two conventional types of TSA. According to the results, both methods are lightweight, and they only consume less than 0.3% of slice registers, 5% of slice LUTs, and 8% of DSP48E1Ss. Furthermore, they are real-time, and can mitigate the attack consequences; however, the PLA architecture has a better performance compared to LA-LUT.