Design and Implementation of Low Power and High- Speed Full Adder

Adder circuit is basic part of arithmetic circuits and also Application Specific Integrated Circuits (ASIC). Combination of different logic styles are used to implement adder circuits. Here, XOR-XNOR and full adder (FA) implemented using PTL, CPL cross coupled and PTL cross coupled logic styles. Performance analysis of these circuits are studied by measuring worst-case delay, power dissipation and Power Delay Product (PDP). Performance of FACs is dependent on XOR-XNOR circuit. The performance analysis of FAC is done by Pyxis schematic, layout by Pyxis layout editor and Design Rule Check (DRC) by Calibre tool in Mentor Graphics EDA tool at 130nm technology operating at 1.2V supply voltage and frequency of 1GHz. CPL cross coupled FAC is having lowest power of 2.65nW; The PTL based FAC 1 and CPL cross coupled FAC has got lowest worst-case delay for sum as 7.99ps and carry as 4.80ps respectively, and CPL cross coupled FAC is lowest PDP of 0.02aJ. CPL cross coupled FAC can be considered as the low power and high-speed FA as it has got lowest PDP. Proposed FAC 1 and FAC 3 have got reduced power dissipation of 4.72nW and 4.29nW. PDP of FAC 1 is 0.20aJ and FAC 3 is 0.16aJ and the number of transistors is 20 and 16 respectively. Proposed transistors and obtained PDP are lesser than PTL based FAC 1 and FAC 2.