Impacts of Independent Dual-Gate Operation on Reliability of Nanosheet Junctionless Thin-Film Transistor

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance (
${G}_{m\_{}{\text {max}}}$
) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage (
${V}_{\text {BG}}$
) operation mode, the
${V}_{\text {BG}}$
can provide a wide threshold voltage (
${V}_{\text {TH}}$
) tuning range ~2 V when the
${V}_{\text {BG}}$
is modulated from 0 to −4 V. The negative
${V}_{\text {BG}}$
bias stress would induce electron injection from the BG, resulting in positive
${V}_{\text {TH}}$
shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative
${V}_{\text {BG}}$
stress, using
${V}_{\text {BG}}$
to modulate the
${V}_{\text {TH}}$
of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent
${V}_{\text {BG}}$
to adjust the
${V}_{\text {TH}}$
of the JL-TFTs to meet the multiple-
${V}_{\text {TH}}$
requirement of advanced integrated circuits.