Method for preparing silicon photonic chip edge packaging structure based on inclined deep etching process

Packaging technology is the core technology for silicon photonic chip engineering applications. The edge structure of silicon photonic chip has the advantages of large bandwidth, low loss, small package volume, and polarization insensitivity, which makes people increasingly hope to make breakthroughs in edge packaging. This paper proposes a method for fabricating silicon photonic chip edge packaging structure based on bevel deep etching process, which can effectively reduce packaging cost. The prior art realizes precise control of the mold spot conversion structure on the edge of the silicon photonic chip through a vertical etching process. The innovation of this paper is that, one is to use the slope formed by plasma etching to match the packaging surface of the optical fiber array to reduce the coupling reflection between the edge of the silicon photonic chip and the optical fiber packaging. The second is to prepare deep silicon etching grooves by a combination of bevel etching process and bosch deep silicon etching process, which improves the redundancy of wafer scribing, and eliminates it by controlling the scribing position in the deep silicon etching groove the step bumps have an adverse effect on the optical fiber packaging, which ultimately reduces the process steps of grinding and polishing the step bumps on the chip end surface in the subsequent packaging process of the edge inverted tapered packaging surface and the inclined array fiber head, so as to completely solve the problem. At this stage, it is necessary to carry out high-precision grinding and polishing for the coupling and packaging of the inverted tapered structure of the silicon photonic chip and the optical fiber array. After testing, the loss of the edge coupler at the wavelength of 1550nm is within the range of 1.5-2.0dB. In addition, the packaging structure can be prepared in the wafer tape-out stage, has the advantages of large-scale production, effectively reducing the cost of silicon photonic chip edge packaging, and has a wide range of engineering application prospects.