Impact of High-Aspect-Ratio Etching Damage on Selective Epitaxial Silicon Growth in 3D NAND Flash Memory

A physical process model for inductive plasma dry etching is presented and applied to simulate vertical channel hole etching, a critical fabrication step in modern 3D NAND flash memory. A specialized advection algorithm is subsequently applied to simulate the selective epitaxial growth (SEG) of silicon on the bottom source line. The induced etching damage on the bottom silicon substrate, which is included in the etching model, is shown to heavily reduce the quality of the SEG. The removal of this damaged layer is shown to result in highly crystalline epitaxially grown silicon.