Machine Learning-Based Verilog-A Modeling for Supply Induced Jitter Sensitivity of High-Speed Memory Interface: Two Layer PCB Case Study

With the ever-increasing demand for both high-performance and high-integrated chips, it is becoming more and more difficult to meet the power distribution network (PDN)-related target specifications. This paper provides the Verilog-A model of supply-induced jitter-aware sensitivity for analyzing supply noise induced timing jitter in DDR high speed interface integrated in cost-effective two-layer circuit board to perform the jitter generated by the supply noise in the time domain compared to present general analysis methods. During design phase, the effort of power distribution network optimization takes place very first to define the floor plan of die, package and circuit board. We propose a Verilog-A model with the skill of vector fitting and neural network for the efficient methodology of timing budget calculation when double data rate (DDR) interface works simultaneously in highly integrated system at early design stage. The goal is to provide adequate performance for cost-effective and system solution and achieving on system-level success.