Analysis of Power Supply Induced Jitter of High Speed Output Buffer with On-Die Low-Dropout Voltage Regulator

In this paper, a methodology to analyze the power supply induced jitter (PSIJ) of high speed output buffer with on-die low-dropout (LDO) voltage regulator is presented. The approach relies on separate analysis of the LDO block and the buffer block. The total system level PSIJ analysis is achieved by combining the stand-alone results together. The AC analysis of power supply rejection ratio (PSRR) of LDO is performed. The loading effect of the buffer is also included. The PSIJ sensitivity analysis of the output buffer is obtained by transient analysis varying the frequency of sinusoidal power rail noise. The system PSIJ sensitivity analysis is completed by multiplying the LDO block PSRR response with the buffer block PSIJ sensitivity. This procedure allows designer to evaluate the system PSIJ with fewer and faster simulations. The contribution of different blocks can be clearly revealed. The proposed approach is validated through Hspice simulation of the entire system level circuit. Reasonably good accuracy has been achieved with the proposed analysis method.