Optimal Power Distribution Network Design for High-Performance Solid-State-Drive Based on Novel Target-Impedance Extraction Method

In this paper, we proposed a novel methodology to offer power distribution network (PDN) design guide for PCB power integrity (PI) design for high performance solid-state-drive (SSD). Compared with conventional target-impedance (Z) formulated by current profile of a chip power model (CPM), the proposed methodology utilizes a measurement based current spectrum and a hierarchical PDN-Z model. In order to solve the fundamental limitations of the narrow-banded CPM current model, we successfully measured the PCB-level current of memory packages consisting of the SSD device and converted the measured current values to the chip-level current values using Y-matrix of the hierarchical PDN-Z model consisting of a PCB, a test interposer, a package, and a chip. High-capacity SSD devices are too expensive to make PCBs for design of experiments to test device performance with current measurement. Therefore, we made a test interposer to measure cost-efficiently a current spectrum for each specific power-domain of a unit package such as a DRAM, a NAND, and a SSD controller that all consisting of a SSD device without disturbing SSD’s normal operations.