Design and Implementation of low power RISC V ISA based coprocessor design for Matrix multiplication

RISC V is an open-source ISA that is used to design the processor and the coprocessor architecture. For fulfilling the requirement of matrix multiplication, a low power and highperformance multiply and accumulate unit has been designed using a modified booth multiplier and carry look-ahead adder. Multiply and accumulate coprocessors are commonly used in all AI/Machine learning, neural network and DSP applications. Further, coprocessor designed here is capable to perform the matrix multiplication for the finite impulse response filter. Development of the low power devices is another challenge. Leakage power plays a significant amount to power dissipation in the CMOS circuits. Power gating methodologies like isolation cells, retention cells and header switches are applied to the logical circuit to reduce the leakage power of the device. The complete architecture is verified for the functionality as well as for the ASIC flow synthesis has been done for different library files. The low power analysis of design is performed through unified power format (UPF) file. The dynamic power reduces by 85.5% after using clock gating whereas the reduction in leakage power is observed to be 40 %.